With the proliferation of battery operated devices, low power operation has become an important criterion in integrated circuit (IC) design. There are several applications where the circuit operates in standby mode for most of the time during operation. The quiescent current for such circuits has to be reduced as much as possible to reduce power consumption. However, reducing quiescent current impacts the transient or dynamic performance of the circuit such as slew rate and settling time. For example, the quiescent current of a reference buffer in a successive approximation analog to digital converter (SAR ADC) with capacitive DAC can be reduced as much as possible so as to just meet the noise and bandwidth specification. However, doing so severely compromises the settling time of the reference buffer as the reference buffer typically needs much higher slew current to charge the DAC capacitance when there is a DAC code change. Increasing the quiescent current to meet the slew requirement will be highly inefficient especially if the circuit is in quiescent state for most of the time.
Dynamic biasing circuits are used to achieve low quiescent power without sacrificing the transient performance. Dynamic biasing circuit works by boosting the current only when required. In the above reference buffer example, when there is a DAC code change, the reference buffer output voltage will reduce. This reduction in output voltage can be sensed by comparing it with the input reference voltage and boosting the bias current of the buffer to meet the slew current requirement.
Figure of merit (FOM) for such a dynamic biasing circuit is the ratio of the quiescent current to the boosted current. Higher FOM means the circuit can achieve higher speed or slew rate for the same quiescent current. Also for a given speed or slew requirement, higher FOM means the quiescent current can be reduced so as to achieve lower power operation.